SA555P These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the time-delay or mono-stable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor.
The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground.
The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.

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Description

These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the time-delay or mono-stable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground. The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.

Not found, similar datasheet recommended

Title

Precision timer for -55 to 85C operation

ECAD Module
Mounting Type: Through Hole
Brand: Texas Instruments
DateCode: 06/
Package / Case: DIP-8
Timer Type: Standard
Package Type: PDIP
Number of Internal Timers: 1
Pin Count: 8
Minimum Operating Supply Voltage: 4.5 V
Maximum Operating Supply Voltage: 16 V
Minimum Operating Temperature: -40 °C
Maximum Operating Temperature: +85 °C
Maximum Quiescent Current: 15mA
Maximum Low Level Output Current: 200mA
Maximum High Level Output Current: -200mA
Height: 4.57mm
Length: 9.81mm
Dimensions: 9.81 x 6.35 x 4.57mm
Width: 6.35mm

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ECAD Module

Product Attributes

The SA555P is a precision timer integrated circuit (IC) manufactured by Texas Instruments. It is a dual-in-line package (DIP-8) that contains two independent 555 timer circuits. Description: The SA555P is a dual precision timer IC that contains two independent 555 timer circuits. It is designed to provide accurate timing and control functions in a wide variety of applications. The SA555P is a low-power device that operates from a single supply voltage of 4.5V to 16V. Features: Low power consumption High accuracy Wide operating voltage range (4.5V to 16V) Low output impedance High frequency stability Low input current High output current capability Low temperature coefficient Low propagation delay Applications: The SA555P is suitable for a wide range of applications including timing, pulse generation, oscillator, and control circuits. It can be used in automotive, industrial, and consumer electronics applications. It is also suitable for use in medical, security, and communication systems. (For reference only)

Preview of the first 3 pages of the data sheet

Document Preview

1 Timing From Microseconds to Hours Astable or Monostable Operation Adjustable Duty Cycle TTL-Compatible Output Can Sink or Source

All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.

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The threshold and trigger levels normally are twothirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flipflop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground.

The output circuit is capable of sinking or sourcing current to 200 mA. Operation is specified for supplies 15 V. With a 5-V supply, output levels are compatible with TTL inputs.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

Updated document to new TI enhanced data sheet format : 1 Deleted Ordering Information table : 1 Added Military Disclaimer to Features list : 1 Added Applications : 1 Added Device Information table : 1 Moved Tstg to Handling Ratings table : 4 Added DISCH switch on-state voltage parameter : 5 Added Device and Documentation Support section : 19 Added ESD warning : 19 Added Mechanical, Packaging, and Orderable Information section : 19

DESCRIPTION
Controls comparator thresholds, Outputs 2/3 VCC, allows bypass capacitor connection
Open collector output to discharge timing capacitor
Active low reset input forces output and discharge low.
End of timing input. THRES > CONT sets output low and discharge low
Start of timing input. TRIG < ½ CONT sets output high and discharge open

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SA555P Electronic Component
SA555P These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the time-delay or mono-stable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground. The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.

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Alternate Names

SA555P

SA555P has several brands around the world that may have alternate names for SA555P due to regional differences or acquisition. SA555P may also be known as the following names: