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Logic - Counters, Dividers

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CD4040BM96

SOP

Texas Instruments

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The ’HC163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the ’HC163 devices is synchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.

Utsource Original Store

≥3:

US $0.46166

US $0.41550

≥50:

US $0.42319

US $0.38087

≥100:

US $0.38472

US $0.34625

From: US $0.38472

CD74ACT163M96E4

SOP16

TI Texas Instruments

1547+

Description: The CD74ACT163M96E4 is a high-speed CMOS logic device from Texas Instruments. It is a 16-bit synchronous binary counter with an asynchronous reset. Features: High-speed CMOS logic 16-

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The ’HC163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the ’HC163 devices is synchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.

Utsource Original Store

≥1:

US $1.61450

US $1.45305

≥5:

US $1.21088

US $1.08979

≥10:

US $0.72653

US $0.65387

≥20:

US $0.70635

US $0.63571

≥50:

US $0.68616

US $0.61755

≥100:

US $0.66598

US $0.59939

≥200:

US $0.64580

US $0.58122

≥500:

US $0.63773

US $0.57396

≥1000:

US $0.62562

US $0.56306

From: US $0.62562

SN74HC163N

DIP-16

Texas Instruments

0230+

SN74HC163N is a synchronous 4-bit binary counter made by Texas Instruments. It is a 16-pin DIP package and is part of the 74HC logic family. Description: The SN74HC163N is a synchronous 4-bit binary

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The ’HC163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the ’HC163 devices is synchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.

Utsource

≥1:

US $0.83820

US $0.75438

≥5:

US $0.62865

US $0.56579

≥10:

US $0.44006

US $0.39605

≥20:

US $0.41910

US $0.37719

≥50:

US $0.37719

US $0.33947

≥100:

US $0.36671

US $0.33004

≥200:

US $0.35624

US $0.32062

≥500:

US $0.34576

US $0.31118

≥1000:

US $0.33528

US $0.30175

From: US $0.33528

74ACT161PC

DIP

National Semiconductor

9312+

Description: The 74ACT161PC is a high-speed 4-bit synchronous binary counter. Features: * High-speed operation * Synchronous counting * Asynchronous reset * Output capability: standard * Inputs are T

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The ’HC163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the ’HC163 devices is synchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.

Utsource Original Store

≥1:

US $0.48090

US $0.43281

≥10:

US $0.28854

US $0.25969

From: US $0.28854

MC74AC4040N

PDIP-16

On Semiconductor

Description: The MC74AC4040N is a dual 4-stage binary ripple counter. Features: - High-speed performance - Low power consumption - Low-voltage operation - Outputs source/sink 24 mA - Outputs c

Counter IC Binary Counter 1 Element 12 Bit Negative Edge 16-DIP

Utsource

≥1:

US $2.46600

US $2.21940

≥5:

US $1.64400

US $1.47960

≥10:

US $1.47960

US $1.33164

≥20:

US $1.43850

US $1.29465

≥50:

US $1.39740

US $1.25766

≥100:

US $1.35630

US $1.22067

≥200:

US $1.31520

US $1.18368

≥500:

US $1.29876

US $1.16888

≥1000:

US $1.27410

US $1.14669

From: US $1.27410

CD40192BE

DIP16

HLF

18+

IC UP/DOWN COUNTR PRESET 16-DIP

US $0.24045

US $0.21641

From: US $0.24045

SN74HC191N

DIP16

HLF

18+

IC 4-BIT UP/DN BIN CNTR 16-DIP

US $0.27480

US $0.24732

From: US $0.27480

74ACT163SCX

SOP16

FSC

06+ROHS

Description: 74ACT163SCX is a high-speed synchronous 4-bit binary counter with synchronous reset. Features: - High-speed synchronous operation - Synchronous reset - Fully static operation - Outputs s

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The ’HC163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the ’HC163 devices is synchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.

Utsource Original Store

≥5:

US $0.23083

US $0.20775

≥100:

US $0.21160

US $0.19044

≥500:

US $0.19236

US $0.17312

From: US $0.19236

SN74HC193N

DIP16

HLF

18+

IC 4-BIT UP/DOWN COUNTER 16-DIP

US $0.27480

US $0.24732

From: US $0.27480

DM7490AN

DIP-14

National Semiconductor

98+

Description: Decade and Binary Counters Features: High Speed: Typical Count Frequency of 100 MHz Asynchronous Master Reset Separate Clock for Each Counter Ripple Clock Inputs Fully Programm

Utsource

≥1:

US $1.24560

US $1.12104

≥5:

US $0.83040

US $0.74736

≥10:

US $0.74736

US $0.67262

≥20:

US $0.72660

US $0.65394

≥50:

US $0.70584

US $0.63526

≥100:

US $0.68508

US $0.61657

≥200:

US $0.66432

US $0.59789

≥500:

US $0.65602

US $0.59042

≥1000:

US $0.64356

US $0.57920

From: US $0.64356

74VHC393MTCX

TSSOP

Fairchild

1021+

Description: The 74VHC393MTCX is a high-speed CMOS dual 4-stage binary ripple counter fabricated with silicon gate C2MOS technology. Features: High speed: tpd = 8.0ns (typ.) at VCC = 5V Low power d

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The ’HC163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the ’HC163 devices is synchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.

Utsource Original Store

≥1:

US $1.09920

US $0.98928

≥5:

US $0.82440

US $0.74196

≥10:

US $0.49464

US $0.44518

≥20:

US $0.48090

US $0.43281

≥50:

US $0.46716

US $0.42044

≥100:

US $0.45342

US $0.40808

≥200:

US $0.43968

US $0.39571

≥500:

US $0.43418

US $0.39077

≥1000:

US $0.42594

US $0.38335

From: US $0.42594

MM74HC393N

DIP14

National Semiconductor

2013+

Description: The MM74HC393N is a high-speed CMOS 4-bit binary counter with dual clock. Features: High Speed Operation: tPD = 10 ns (TYP.) at VCC = 5 V Low Power Consumption: ICC = 1 μA (MAX) at Ta =

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The ’HC163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the ’HC163 devices is synchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.

Utsource Original Store

≥1:

US $0.82440

US $0.74196

≥5:

US $0.61830

US $0.55647

≥10:

US $0.43281

US $0.38953

≥20:

US $0.41220

US $0.37098

≥50:

US $0.37098

US $0.33388

≥100:

US $0.36068

US $0.32461

≥200:

US $0.35037

US $0.31533

≥500:

US $0.34007

US $0.30606

≥1000:

US $0.32976

US $0.29678

From: US $0.32976

SN74LS191N

DIP16

HLF

18+

Description: 4-Bit Synchronous Up/Down Counter Features: - Synchronous operation - Counts up or down - Ripple carry output - Asynchronous master reset - Inputs and outputs fully buffered - Outp

IC SYNC UP/DOWN COUNTER 16-DIP

US $0.27480

US $0.24732

From: US $0.27480

MM74HC4040M

SOP-16

FSC

05+

Alternator Voltage Regulator Darlington Driver; Package: SOIC 14 LEAD; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2500

Utsource

≥1:

US $0.64800

US $0.58320

≥10:

US $0.38880

US $0.34992

≥100:

US $0.34560

US $0.31104

≥1000:

US $0.33480

US $0.30132

≥2500:

US $0.32400

US $0.29160

≥5000:

US $0.31320

US $0.28188

≥10000:

US $0.30240

US $0.27216

From: US $0.30240

CD4029BCN

DIP-16

Ns/fsc

00+

Presettable Binary/Decade Up/Down Counter

Utsource

≥1:

US $2.86860

US $2.58174

≥5:

US $1.91240

US $1.72116

≥10:

US $1.72116

US $1.54904

≥20:

US $1.67335

US $1.50602

≥50:

US $1.62554

US $1.46299

≥100:

US $1.57773

US $1.41996

≥200:

US $1.52992

US $1.37693

≥500:

US $1.51080

US $1.35972

≥1000:

US $1.48211

US $1.33390

From: US $1.48211

CD4020BCM

SOP

FAI

99+

Description: The CD4020BCM is a 14-stage ripple-carry binary counter/divider and oscillator. Features: High Speed Operation Low Power Consumption Wide Operating Temperature Range Low Input

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The ’HC163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the ’HC163 devices is synchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.

Utsource Original Store

≥3:

US $0.46166

US $0.41550

≥50:

US $0.42319

US $0.38087

≥100:

US $0.38472

US $0.34625

From: US $0.38472

74F160APC

DIP-16

FSC

00+

Utsource

≥1:

US $2.09550

US $1.88595

≥5:

US $1.39700

US $1.25730

≥10:

US $1.25730

US $1.13157

≥20:

US $1.22238

US $1.10014

≥50:

US $1.18745

US $1.06871

≥100:

US $1.15252

US $1.03727

≥200:

US $1.11760

US $1.00584

≥500:

US $1.10363

US $0.99327

≥1000:

US $1.08268

US $0.97441

From: US $1.08268

CD4040BCN

DIP

Fairchild

9824+

Description: The CD4040BCN is a CMOS 12-stage ripple carry binary counter/divider and oscillator. Features: High speed operation Low power consumption High noise immunity High output drive capabi

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The ’HC163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the ’HC163 devices is synchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.

Utsource Original Store

≥1:

US $2.47320

US $2.22588

≥5:

US $1.64880

US $1.48392

≥10:

US $1.48392

US $1.33553

≥20:

US $1.44270

US $1.29843

≥50:

US $1.40148

US $1.26133

≥100:

US $1.36026

US $1.22423

≥200:

US $1.31904

US $1.18714

≥500:

US $1.30255

US $1.17230

≥1000:

US $1.27782

US $1.15004

From: US $1.27782

SN74HC161N

DIP16

HLF

18+

IC 4-BIT BINARY COUNTER 16-DIP

US $0.24045

US $0.21641

From: US $0.24045

74AC169PC

DIP-16

Ns/fsc

Synchronous Up/Down Counter

Utsource

≥1:

US $1.63920

US $1.47528

≥5:

US $1.09280

US $0.98352

≥10:

US $0.98352

US $0.88517

≥20:

US $0.95620

US $0.86058

≥50:

US $0.92888

US $0.83599

≥100:

US $0.90156

US $0.81140

≥200:

US $0.87424

US $0.78682

≥500:

US $0.86331

US $0.77698

≥1000:

US $0.84692

US $0.76223

From: US $0.84692
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