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TSSOP48
02+
Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs; Package: TSSOP; No of Pins: 48; Container: Rail
Stock:10000
Minimum:2
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Description: The 74AC74SC is a dual D-type flip-flop with a clock (CP) and a reset (R) input. It is a high-speed CMOS device with a propagation delay of 8.5 ns. Features: High-speed CMOS Low po
Stock:10000
Minimum:2
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SOP-20
TI9
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with an enable input. The 'LS377, 'LS378, and 'LS379 devices are similar to 'LS273, 'LS174, and 'LS175, respectively, but feature a common enable instead of a common clear. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G\ input. These flip-flops are guaranteed to respond to clock frequencies ranging from 0 to 30 MHz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 10 milliwatts per flip-flop.
Stock:10000
Minimum:3
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SOP-20
FSC
Octal D Flip-Flop with Clear; Package: SOIC-Wide; No of Pins: 20; Container: Rail
Stock:10000
Minimum:6
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Description: The 74ACTQ18823SSC is a high-speed CMOS octal bus transceiver featuring non-inverting 3-state outputs and is designed for 2.7V to 3.6V VCC operation. Features: - High-speed operation: tp
Stock:5000
Minimum:1
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TSSOP14
FSC
MR, Active low P-P internal pullup, Active high P-P, -40C to +125C, 5-SOT-23, T/R
Stock:10000
Minimum:3
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The NL17SZ74USG is a high-speed, low-power, single-pole double-throw (SPDT) analog switch from ON Semiconductor. It is designed for use in applications requiring low on-resistance and low power consum
Stock:10000
Minimum:3
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Description: The 74HC174D is a high-speed CMOS logic device containing four D-type flip-flops with individual data, set, reset, and clock inputs. The device is designed for 2-V to 6-V VCC operation.
Stock:10000
Minimum:2
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DIP-16
National Semiconductor
Zener Diode 225 mW 2.4 V ±5%SOT-23; Package: SOT-23 TO-236 3 LEAD; No of Pins: 3; Container: Tape and Reel; Qty per Container: 10000
Description: Quad D-Type Flip-Flop Features: Low power consumption High noise immunity High speed operation Inputs accept voltages up to 5.5V Outputs source/sink 24mA Compatible with TTL
Stock:10000
Minimum:3
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Stock:10000
Minimum:4
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DIP-20
National Semiconductor
88+
Octal D-Type Flip-Flop with Clock Enable; Package: DIP; No of Pins: 20; Container: Rail
Stock:10000
Minimum:2
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SOP20
FSC
Octal D-Type Flip-Flop; Package: SOIC-Wide; No of Pins: 20; Container: Rail
Stock:10000
Minimum:3
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DIP-14
Ti/mot
500mA, 5V,±4% Tolerance, Negative Voltage Regulator, Ta = 0°C to +125°C; Package: TO-220, SINGLE GAUGE; No of Pins: 3; Container: Rail; Qty per Container: 50
Description: The SN74LS73AN is a dual positive edge-triggered J-K flip-flop with individual J, K, clock, set and reset inputs, and complementary Q and Q outputs. Features: - Positive edge-triggere
Stock:10000
Minimum:2
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DIP
STMicroelectronics
Low-Voltage Adjustable Precision Shunt Regulator 3-TO-92 -40 to 85
Description: The M74HC74B1R is a dual D-type flip-flop with reset. It has two independent D-type flip-flops with complementary outputs. The flip-flops are edge-triggered and are clocked by the positiv
Stock:10000
Minimum:2
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DIP-14
Fairchild
Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs
Description: The DM74LS74AN is a dual D-type flip-flop with individual data (D) and clock (CP) inputs, set (S) and reset (R) inputs, and complementary Q and Q outputs. Features: Positive-edge trigg
Stock:10000
Minimum:3
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Stock:10000
Minimum:2
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DIP-16
Texas Instruments
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
Description: Dual JK Flip-Flop Features: Positive-Edge Triggering Outputs Source/Sink 24 mA Outputs Can Be Used as Inputs to Other Gates Latch-Up Performance Exceeds 250 mA Per JESD 78, Clas
Stock:10000
Minimum:2
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Stock:10000
Minimum:3
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Description: The MM74C107N is a dual J-K flip-flop with reset in a 14-pin DIP package. Features: High Speed Operation Low Power Consumption Positive Edge-Triggered Inputs Reset Inputs
Stock:10000
Minimum:2
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Stock:10000
Minimum:3
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Stop production experts, we can provide a large number of electronic components that have been stopped production and are difficult to find, to facilitate the maintenance company