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FE2010A Peripheral IC
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FE2010A

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Description

Peripheral IC

  • ECAD Module
  • Brand: Faraday
  • Package / Case: PLCC-84

All product names, trademarks, brands and logos used on this site are the property of their respective owners. The depiction, description or sale of products featuring these names, trademarks, brands and logos is for identification purposes only and is not intended to indicate any affiliation with or authorization by any rights holder.

ECAD Module

Product Attributes

  • Part: FE2010A Package: PLCC-84 Manufacturer: Faraday Technology Corporation Description: The Faraday FE2010A is a single-chip, low-power 32-bit RISC processor. It is designed to deliver high performance at low power consumption. It features a high-performance instruction set and advanced pipeline architecture designed to reduce power consumption while delivering better performance. Features: 32-bit RISC CPU core High performance and low power consumption Supports both 8 and 16-bit instruction sets 32-bit instruction and data buses Single cycle instruction execution 5-stage pipelined architecture Memory mapped I/O (MMIO) Multiple clock domains Low power modes Clock frequency up to 40MHz JTAG boundary scan Applications: The FE2010A is suitable for various applications, including but not limited to: Industrial Automation Networking and Communication Automotive Consumer Electronics Medical Electronics Security and Surveillance (For reference only)

Description

In computer or CPU based applications there is always an interface present that connects the input / output devices to the computer. This interface provides the communication link between devices and computer.

FE2010A is a PC Bus, CPU and peripheral controller. It is an enhanced version of FE2010. Main difference between FE2010A and FE2010 is that, FE2010A can support higher clock frequencies. It was one of the earliest chipset that were used in computers. FE2010A was used in IBM and Intel motherboards.

 

Pin Description

FE2010A is available in Plastic Leaded Chip Carrier (PLCC) package. J-type leads are available on all four sides of the IC. It is in square type configuration and occupies less size compared to the pins available on the IC. Pin diagram of the IC is given below.

SupplierFile/202006/15/f_766404270d194115b4d80a03cbd2e262.png

Pin Number

I/ O

Pin Name

Description

1

-

VDD

Power

2

-

VSS

Ground

3

O

RS2

RAS 2, Active high

4

O

RS3

RAS 3, Active high

5

O

NRAM

RAM Decode, Active low

6

O

NEPSL

PROM decode, Active low

7

O

NBIOCS

BIOS ROM enable, Active low

8

O

SLAD

Address select, Active high

9

O

NUSCS

User PROM select, Active low

10

O

INT

Interrupt, Active high

11

I

A64K

RAM type select

12

I

VIDO

Video type 0

13

I

VID1

Video type 1

14

O

Speaker

Data to speaker

15

I

NREST

Reset in, Active low

16

I

-

Unused

17

O

Ready

Ready to CPU, Active high

18

O

Clear

Reset to CPU, Active high

19

O

Clock

Clock to CPU, Active high

20

O

OSC

OSC to expansion bus

21

O

X2

Crystal output

22

-

VSS

Ground

23

I

X1

Crystal input

24

I/O

NRQGT

Request to CPU, Active low

25

I/O

KBCLK

Keyboard clock

26

I/O

KBDA

Keyboard data, Active high

27

I

NIOCK

EEPROM from expansion

28

I

IORDY

Ready from expansion

29

I

APNMI

NMI from co-processor

30

O

AEN

DMA cycle, Active high

31

O

NMI

Non mask able interrupt, Active high

32

I

PTYN

Parity bit from RAM

33

O

PTYOUT

Parity bit to RAM

34

I/O

AD-0

Address data bus bit 0

35

I/O

AD-1

Address data bus bit 1

36

I/O

AD-2

Address data bus bit 2

37

I/O

AD-3

Address data bus bit 3

38

I/O

AD-4

Address data bus bit 4

39

I/O

AD-5

Address data bus bit 5

40

I/O

AD-6

Address data bus bit 6

41

I/O

AD-7

Address data bus bit 7

42

-

VSS

Ground

43

-

VDD

Power

44

I/O

A-8

Address bit 8

45

I/O

A-9

Address bit 9

46

I

A-10

Address bit 10

47

I

A-11

Address bit 11

48

I

A-12

Address bit 12

49

I/O

A-13

Address bit 13

50

I/O

A-14

Address bit 14

51

I/O

A-15

Address bit 15

52

I/O

A-16

Address bit 16

53

I/O

A-17

Address bit 17

54

I/O

A-18

Address bit 18

55

I/O

A-19

Address bit 19

56

I

DRQ3

DMA request line 3, Active high

57

I

DRQ2

DMA request line 2, Active high

58

I

DRQ1

DMA request line 1, Active high

59

O

EOP

End of process

60

O

NDAK3

DMA acknowledge for channel 3

61

O

NDAK2

DMA acknowledge for channel 2

62

O

NDAK1

DMA acknowledge for channel 1

63

O

NDAK0

DMA acknowledge for channel 0

64

-

VSS

Ground

65

O

NIOR

Read command, Active high

66

O

NIOW

Write command, Active low

67

O

NMEMR

Memory read, Active low

68

O

NMEMW

Memory write, Active low

69

O

BALE

Address latch enable

70

O

ALE

Address lath enable

71

O

NDEN

Data enable

72

O

DTR

Data transmit

73

I

S2

CPU status Bit

74

I

S1

CPU status Bit

75

I

S0

CPU status Bit

76

I

IRQ2

Interrupt request

77

I

IRQ3

Interrupt request

78

I

IRQ4

Interrupt request

79

I

IRQ5

Interrupt request

80

I

IRQ6

Interrupt request

81

I

IRQ7

Interrupt request

82

O

CAS

RAM CAS, Active high

83

O

RS0

RAS0, Active high

84

O

RS1

RAS1, Active high

 

IC Electrical Characteristics/ Specifications

Parameter

Description

Value

VDD

Power supply voltage

-0.5V to +7V

VI

Input voltage

-0.5V to +0.3V

VO

Output voltage

-0.5V to +0.3V

TSTG

Storage temperature

-65℃ to 150

CI

Input capacitance

15pF at 1MHz

CIO

I/O capacitance

15pF at 1MHz

 

SBC design using FE2010A

Block diagram of single board computer using 8088 microprocessors is shown in figure below

SupplierFile/202006/15/f_af1293ff3f1e46b29cf93c01fd04a5e5.png

Some Part number from the same manufacture

FE2010A
Peripheral IC
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