TLC1549CP

D 10-Bit-Resolution A/D Converter D Inherent Sample and Hold D Total Unadjusted Error. ± 1 LSB Max D On-Chip System Clock D Terminal Compatible With TLC549 and

description

The TLC1549C, TLC1549I, and TLC1549M are 10-bit, switched-capacitor, successiveapproximation analog-to-digital converters. These devices have two digital inputs and a 3-state output [chip select (CS), input-output clock (I/O CLOCK), and data output (DATA OUT)] that provide a three-wire interface to the serial port of a host processor.

The sample-and-hold function is automatic. The converter incorporated in these devices features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows lowerror conversion over the full operating free-air temperature range.

The TLC1549C is characterized for operation from to 70°C. The TLC1549I is characterized for operation from to 85°C. The TLC1549M is characterized for operation over the full military temperature range to 125°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
DESCRIPTION

I Analog signal input. The driving source impedance should 1 k. The external driving source to ANALOG IN should have a current capability 10 mA.

5 I Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT and

I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system clock. A low-to-high

transition disables I/O CLOCK within a setup time plus two falling edges of the internal system clock.

6 O This 3-state serial output for the A/D conversion result is in the high-impedance state when CS is high and active when CS is low. With a valid chip select, DATA OUT is removed from the high-impedance state and is driven to the logic level corresponding to the MSB value of the previous conversion result. The next falling edge of I/O CLOCK drives DATAOUT to the logic level corresponding to the next most significant bit, and the remaining bits are shifted out in order with the LSB appearing on the ninth falling edge of I/O CLOCK. On the tenth falling edge of I/O CLOCK, DATA OUT is driven to a low logic level so that serial interface data transfers of more than ten clocks produce zeroes as the unused LSBs.

The ground return for internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.

I/O CLOCK 7 I Input/output clock. I/O CLOCK receives the serial I/O CLOCK input and performs the following three functions: 1) On the third falling edge of I/O CLOCK, the analog input voltage begins charging the capacitor array and continues do so until the tenth falling edge of I/O CLOCK. 2) It shifts the nine remaining bits of the previous conversion data out on DATA OUT. 3) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock.

I The upper reference voltage value (nominally VCC) is applied to REF The maximum input voltage range is

determined by the difference between the voltage applied to REF + and the voltage applied to REF
3 I The lower reference voltage value (nominally ground) is applied to REF

With chip select (CS) inactive (high), I/O CLOCK is initially disabled and DATA OUT is in the high impedance state. When the serial interface takes CS active (low), the conversion sequence begins with the enabling of I/O CLOCK and the removal of DATA OUT from the high-impedance state. The serial interface then provides the I/O CLOCK sequence to I/O CLOCK and receives the previous conversion result from DATA OUT. I/O CLOCK receives an input sequence that is between 10 and 16 clocks long from the host serial interface. The first ten I/O clocks provide the control timing for sampling the analog input.

There are six basic serial interface timing modes that can be used with the TLC1549. These modes are determined by the speed of I/O CLOCK and the operation CS as shown in Table 1. These modes are (1) a fast mode with a 10-clock transfer and CS inactive (high) between transfers, (2) a fast mode with a 10-clock transfer and CS active (low) continuously, (3) a fast mode with to 16-clock transfer and CS inactive (high) between transfers, (4) a fast mode with a 16-bit transfer and CS active (low) continuously, (5) a slow mode with to 16-clock transfer and CS inactive (high) between transfers, and (6) a slow mode with a 16-clock transfer and CS active (low) continuously.

The MSB of the previous conversion appears on DATA OUT on the falling edge CS in mode 1, mode 3, and mode 5, within 21 µs from the falling edge of the tenth I/O CLOCK in mode 2 and mode 4, and following the sixteenth clock falling edge in mode 6. The remaining nine bits are shifted out on the next nine falling edges of I/O CLOCK. Ten bits of data are transmitted to the host serial interface through DATA OUT. The number of serial clock pulses used also depends on the mode of operation, but a minimum of ten clock pulses is required for conversion to begin. On the tenth clock falling edge, the internal logic takes DATA OUT low to ensure that the remaining bit values are zero if the I/O CLOCK transfer is more than ten clocks long.

Table 1 lists the operational modes with respect to the state of CS, the number of I/O serial transfer clocks that can be used, and the timing on which the MSB of the previous conversion appears at the output.