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製品の説明
ENHANCED Z180 MICROPROCESSOR
このサイトで使用されているすべての製品名、商標、ブランド、ロゴは、それぞれの所有者の財産です。 これらの名前、商標、ブランド、およびロゴを使用した製品の描写、説明、または販売は、識別のみを目的としており、権利所有者との提携または許可を示すことを意図したものではありません。
FEATURES
● Code Compatible with Zilog Z80 CPU
● Extended Instructions
● Two Chain-Linked DMA Channels
● Low Power-Down Modes
● On-Chip Interrupt Controllers
● Three On-Chip Wait-State Generators
● On-Chip oscillator/Generator
● Expanded MMU Addressing (up to 1 MB)
● Clocked Serial 10 Port
● Two 16-Bit Counter/Timers
● Two Enhanced UARTS (up to 512 Kbps)
● Clock Speeds:6, 8, 10, 20, 33 MHz
● Operating Range: 5V (3.3V@ 20 MHz)
● Operating Temperature Range: 0℃ to +70℃
● -40°C to +85 °C Extended Temperature Range
● Three Packaging Styles
— 68-Pin PLCC
— 64-Pin DIP
— 80-Pin QFP
GENERAL DESCRIPTION
The enhanced Z80180/Z8S180/Z8L180 significantly improves on the previous Z801 80 models while still providing full backward compatibility with existing Zilog Z80 devices. The Z80180/Z8S180/Z8L180 now offers faster execution speeds, power saving modes, and EMI noise reduction.
This enhanced Z180 design also incorporates additional feature enhancements to the ASCIs, DMAs, and Icc STANDBY Mode power consumption. With the addition of “ESCC-like" Baud Rate Generators (BRGs), the two ASCIs now have the flexibility and capability to transfer data asynchronously at rates of up to 512 Kbps. In addition, the ASCI receiver has added a 4-byte First In First Out (FIFO) which can be used to buffer incoming data to reduce the incidence of overrun errors. The DMAs have been modified to allow for a“chain-linking" of the two DMA channels when set to take their DMA requests from the same peripherals device. This feature allows for non-stop DMA operation between the two DMA channels, reducing the amount of CPU intervention .
Not only does the Z80180/Z8S180/Z8L 180 consume less power during normal operations than the previous model, it has also been designed with three modes intended to further reduce the power consumption. Zilog reduced lcc power consumption during STANDBY Mode to a minimum of 10 xA by stopping the external oscillators and internal clock. The SLEEP mode reduces power by placing the CPU into a "stopped" state, thereby consuming less current while the on-chip l/O device is still operating. The SYSTEM STOP mode places both the CPU and the on-chip peripherals into a“stopped" mode, thereby reducing power consumption even further.
A new clock doubler feature has been implemented in the Z80180/Z8S180/Z8L 180 device that allows the programmer to double the internal clock from that of the external clock. This provides a systems cost savings by allowing the use of lower cost, lower frequency crystals instead of the higher cost, and higher speed oscillators.
The Enhanced Z180 is housed in 80-pin QFP, 68-pin PLCC, and 64-pin DIP packages.
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Japan からの 44 件のバイヤーレビュー
Kimberly Edwards
Length of registration:7 years
I recently tested the Utsource Z8S18033VSC integrated circuit and was very impressed with its performance. It was easy to install and configure, and the results were very reliable. I found that the circuit was able to handle a wide range of tasks with ease, and the overall performance was excellent. I would definitely recommend this product to anyone looking for a reliable and efficient integrated
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03/17/2023
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Z8S18033VSC
Z8S18033VSCには世界中にいくつかのブランドがあり、地域の違いや買収によりZ8S18033VSCの別名が付けられる場合があります。 Z8S18033VSCは次の名前でも知られています。
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