3.3V Operation ACPI 3.0 Compliant PC2001 compliant VTR (standby) and VBAT Power Planes
- Low Standby Current in Sleep Mode Connected Standby Support 32kHz Clock Source
- 32kHz Crystal (XTAL) Supported - Single-Ended 32kHz Clock Source LPC Host Interface - LPC Specification 1.1 Compatible - LPC I/O and Memory Cycles Decoded - Supports optional signals: CLKRUN#, LPCPD#, SERIRQ, SMI#, EC_SCI# (ACPI PME Event) - Supports 19.2 MHz to 33 MHz nominal bus clock speeds Configuration Register Set - Compatible with ISA Plug-and-Play Standard - EC-Programmable Base Address 8042 Emulated Keyboard Controller - 8042 Style Host Interface - Port 92 Legacy A20M Support - Fast GATEA20 & Fast CPU_RESET System to EC Message Interface - One Embedded Memory Interface - Host Serial or Parallel IRQ Source - Provides Two Windows to On-Chip SRAM for
Host Access - Two Register Mailbox Command Interface - Mailbox Registers Interface - Thirty-two 8-Bit Scratch Registers - Two Register Mailbox Command Interface - Two Register SMI Source Interface - Five ACPI Embedded Controller Interfaces - Four EC Interfaces - One Power Management Interface
Deep Sleep States Trace FIFO Debug Port (TFDP) Internal DMA Controller
- Hardware or Firmware Flow Control - Firmware Initiated Memory-to-Memory transfers - 7-Hardware DMA Channels support three
SMBus Master/Slave Controllers and one SPI Controller - Hardware CRC-32 Generator on Channel 0 Secure Boot ROM Loader - 4 Code Images in Shared Flash Supported - Crisis Recovery over Keyboard matrix Scan Pins - Supports CRC-32 and AES-128 Encryption Vectored Interrupt Controller - Maskable Interrupt controller - Maskable Hardware Wake-Up Events - Supports legacy aggregated mode - Supports Vector Generation per Status Bit Programmable 16-bit Counter/Timer Interface - Four 16-bit Auto-reloading Counter/Timer Instances - Two Operating Modes per Instance: Timer and One-shot. 32-bit RTOS Timer - Runs Off 32kHz Clock Source - Continues Counting in all the Chip Sleep States Regardless of Processor Sleep State - Counter is Halted when Embedded Controller is Halted (e.g., JTAG debugger active, break points) - Generates wake-capable interrupt event Watch Dog Timer (WDT) Hibernation Timer Interface - One 32.768 KHz Driven Timer - Programmable Wake-up from to 128 Minutes Week Timer - System Power Present Input Pin
- Week Alarm Event only generated when System Power is Available
- Power-up Event - Week Alarm Interrupt with 1 Second to 8.5 Year
Time-out - Sub-Week Alarm Interrupt with 0.50 Seconds -
72.67 hours time-out - 1 Second and Sub-second Interrupts Battery-Powered General Purpose Output (BGPO) VBAT-Powered Control Interface (VCI) - 2 Active-low VCI Inputs - 1 Active-high VCI Input - 1 Active-high VCI Output Pin - Optional filter and latching
Power-Fail Status Register Port 80 BIOS Debug Port
- Two Ports, Assignable to Any LPC IO Address - 24-bit Timestamp with Adjustable Timebase - 16-Entry FIFO PECI Interface 3.0 Two Programmable Comparators - 8 Bit Resolution - Independent Outputs per Comparator - Option to Use Pin or Programmable Voltage Ref-
erence Input - Can be used for Thermistor Voltage Sensing Integrated Standby Power Reset Generator XNOR Test Mode
Enhanced Serial Peripheral Interface (eSPI) - Intel eSPI Specification compliant - Supports four channels/interfaces: - Peripheral channel Interface - Virtual Wire Interface - Out of Band Channel Interface - Flash Channel Interface - Supports EC Bus Master to Host Memory
Internal Memory - Boot ROM 32 kB Data Optimized SRAM - Code Optimized SRAM Options from - 64 Bytes Battery Powered SRAM
Keyboard Matrix Scan Controller - Supports 18x8 Matrix - Pre-Drive Mode Supported
Up To Three EC-based SMBus 2.0 Host Controllers - Allows Master or Dual Slave Operation - Controllers are Fully Operational on Standby Power - I2C Datalink Compatibility Mode - Multi-Master Capable - Supports Clock Stretching - Programmable Bus Speeds - 1 MHz Capable - SMBus Time-outs Interface to 6 Port Flexible Multiplexing to 5 ports with or 3.3V Configurable Input Threshold - 1 port with VTT level signaling (i.e., AMD SBTSI Port) - Supports DMA Network Layer
- Independent Hardware Driven PS/2 Ports - Fully functional on Main and/or Suspend Power - PS/2 Edge Wake Capable - 3.6V Tolerant I/O Suitable for Internal Board
- Inputs - Asynchronous rising and falling edge wakeup detection Interrupt High or Low Level
- Outputs: - Push Pull or Open Drain output - Programmable power well emulation
- Pull up or pull down resistor control - Automatically disabling pull-up resistors when output driven low - Automatically disabling pull-down resistors when output driven high
- Group- or individual control of GPIO data. Up To Three LEDs
- Programmable Blink Rates - Piecewise Linear Breathing LED Output Control-
waveforms - Operational in EC Sleep States One Serial Peripheral Interface (SPI) Controller - Master Only SPI Controller - Mappable to three ports (only 1 port active at a
time) - 1 shared SPI Interface. - 1 General Purpose SPI Interface (package
Keyboard Matrix Scan connector) - Dual and Quad I/O Support
- Flexible Clock Rates - SPI Burst Capable - SPI Controller Operates with Internal DMA Con-
troller with CRC Generation Up To Two BC-Link Interconnection Bus ADC Interface
to 8 Channels - 10-bit Conversion 10s - Integral Non-Linearity of ±0.5 LSB; Differential
Non-Linearity of ±0.5 LSB - External Analog Voltage Reference DAC Interface to 2 Channels - 8 Bit Resolution - External Analog Voltage Reference FAN Support to 8 Programmable Pulse-Width Modulator
(PWM) Outputs, for Fan or General Use - Multiple Clock Rates & 16-Bit OFF Counters
- Full function Serial Port or 2-Pin Debug Port (product dependent)
- High Speed NS16C550A Compatible UART with Send/Receive 16-Byte FIFOs
- Programmable Main Power or Standby Power Functionality
- Standard Baud Rates to 115.2 Kbps, Custom Baud Rates to 1.5 Mbps
- 128 VTQFP RoHS Compliant Package - 144 WFBGA RoHS Compliant Package
This table shows the total number of instances available per product. However, not all features may be used simultaneously since they are multiplexed on the same pins. See the Pin Description chapter to determine specific chip configuration options.
LPC I2C eSPI LPC I2C eSPI LPC I2C eSPI
Required
