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Logic - Counters, Dividers

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CD4040BM96

SOP

Texas Instruments

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or

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PHP28.01898

PHP25.21708

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PHP25.68407

PHP23.11566

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PHP23.34915

PHP21.01424

From: PHP23.34915

SN74S163N

DIP-16

Texas Instruments

SN74S163N is a synchronous 4-bit binary counter with a synchronous reset produced by Texas Instruments. It is a 16-pin dual in-line package (DIP-16). Description: The SN74S163N is a synchronous 4-bit

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or

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PHP36.62740

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PHP30.52285

PHP27.47053

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PHP21.36573

PHP19.22911

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PHP18.31366

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PHP18.31357

PHP16.48225

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PHP17.80498

PHP16.02444

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PHP17.29638

PHP15.56671

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PHP15.10899

≥1000:

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PHP14.65076

From: PHP16.27861

CD74ACT163M96E4

SOP16

TI Texas Instruments

1547+

Description: The CD74ACT163M96E4 is a high-speed CMOS logic device from Texas Instruments. It is a 16-bit synchronous binary counter with an asynchronous reset. Features: High-speed CMOS logic 16-

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or

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PHP88.18775

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PHP66.14081

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PHP44.09387

PHP39.68447

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PHP42.86904

PHP38.58214

≥50:

PHP41.64421

PHP37.47981

≥100:

PHP40.41938

PHP36.37748

≥200:

PHP39.19455

PHP35.27507

≥500:

PHP38.70464

PHP34.83418

≥1000:

PHP37.96972

PHP34.17274

From: PHP37.96972

SN74HC163N

DIP-16

Texas Instruments

0230+

SN74HC163N is a synchronous 4-bit binary counter made by Texas Instruments. It is a 16-pin DIP package and is part of the 74HC logic family. Description: The SN74HC163N is a synchronous 4-bit binary

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The ’HC163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the ’HC163 devices is synchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.

Utsource

≥1:

PHP50.87147

PHP45.78435

≥5:

PHP38.15360

PHP34.33826

≥10:

PHP26.70784

PHP24.03704

≥20:

PHP25.43573

PHP22.89218

≥50:

PHP22.89218

PHP20.60296

≥100:

PHP22.25608

PHP20.03049

≥200:

PHP21.62065

PHP19.45860

≥500:

PHP20.98463

PHP18.88613

≥1000:

PHP20.34854

PHP18.31366

From: PHP20.34854

CD40192BE

DIP-16

Ti/rca

CMOS PRESETTABLE UP/DOWN COUNTERS(DUAL CLOCK WITH RESET)

Utsource

≥1:

PHP186.52862

PHP167.87574

≥5:

PHP177.20214

PHP159.48188

≥10:

PHP167.87574

PHP151.08820

≥20:

PHP163.21224

PHP146.89102

≥50:

PHP158.54933

PHP142.69443

≥100:

PHP153.88642

PHP138.49775

≥200:

PHP149.22285

PHP134.30057

≥500:

PHP147.35784

PHP132.62202

≥1000:

PHP144.55936

PHP130.10340

From: PHP144.55936

74ACT161PC

DIP

National Semiconductor

9312+

Description: The 74ACT161PC is a high-speed 4-bit synchronous binary counter. Features: * High-speed operation * Synchronous counting * Asynchronous reset * Output capability: standard * Inputs are T

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or

Utsource Original Store

≥1:

PHP29.18644

PHP26.26780

≥10:

PHP17.51186

PHP15.76068

From: PHP17.51186

CD40192BE

DIP16

HLF

18+

IC UP/DOWN COUNTR PRESET 16-DIP

PHP14.59322

PHP13.13390

From: PHP14.59322

SN74HC191N

DIP16

HLF

18+

IC 4-BIT UP/DN BIN CNTR 16-DIP

PHP16.67797

PHP15.01017

From: PHP16.67797

74ACT163SCX

SOP16

FSC

06+ROHS

Description: 74ACT163SCX is a high-speed synchronous 4-bit binary counter with synchronous reset. Features: - High-speed synchronous operation - Synchronous reset - Fully static operation - Outputs s

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or

Utsource Original Store

≥5:

PHP14.00949

PHP12.60854

≥100:

PHP12.84203

PHP11.55783

≥500:

PHP11.67458

PHP10.50712

From: PHP11.67458

74HC393D

SOP-14

Philips

Description: The 74HC393D is a dual 4-stage static shift register with output registers. It has two independent 4-bit shift registers with complementary serial outputs (QA and QB) and common clock (CP

Utsource

≥1:

PHP43.54600

PHP39.19139

≥5:

PHP34.83677

PHP31.35308

≥10:

PHP20.03115

PHP18.02805

≥20:

PHP17.41838

PHP15.67654

≥50:

PHP15.67654

PHP14.10889

≥100:

PHP15.24083

PHP13.71671

≥200:

PHP14.80561

PHP13.32503

≥500:

PHP14.37049

PHP12.93343

≥1000:

PHP13.93469

PHP12.54125

From: PHP13.93469

SN74HC193N

DIP16

HLF

18+

IC 4-BIT UP/DOWN COUNTER 16-DIP

PHP16.67797

PHP15.01017

From: PHP16.67797

74VHC393MTCX

TSSOP

Fairchild

1021+

Description: The 74VHC393MTCX is a high-speed CMOS dual 4-stage binary ripple counter fabricated with silicon gate C2MOS technology. Features: High speed: tpd = 8.0ns (typ.) at VCC = 5V Low power d

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or

Utsource Original Store

≥1:

PHP66.71186

PHP60.04068

≥5:

PHP50.03390

PHP45.03051

≥10:

PHP30.02034

PHP27.01830

≥20:

PHP29.18644

PHP26.26780

≥50:

PHP28.35254

PHP25.51729

≥100:

PHP27.51864

PHP24.76678

≥200:

PHP26.68475

PHP24.01627

≥500:

PHP26.35119

PHP23.71607

≥1000:

PHP25.85085

PHP23.26576

From: PHP25.85085

MM74HC393N

DIP14

National Semiconductor

2013+

Description: The MM74HC393N is a high-speed CMOS 4-bit binary counter with dual clock. Features: High Speed Operation: tPD = 10 ns (TYP.) at VCC = 5 V Low Power Consumption: ICC = 1 μA (MAX) at Ta =

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or

Utsource Original Store

≥1:

PHP50.03390

PHP45.03051

≥5:

PHP37.52542

PHP33.77288

≥10:

PHP26.26780

PHP23.64102

≥20:

PHP25.01695

PHP22.51525

≥50:

PHP22.51525

PHP20.26373

≥100:

PHP21.88983

PHP19.70085

≥200:

PHP21.26441

PHP19.13797

≥500:

PHP20.63898

PHP18.57508

≥1000:

PHP20.01356

PHP18.01220

From: PHP20.01356

SN74LS191N

DIP16

HLF

18+

Description: 4-Bit Synchronous Up/Down Counter Features: - Synchronous operation - Counts up or down - Ripple carry output - Asynchronous master reset - Inputs and outputs fully buffered - Outp

IC SYNC UP/DOWN COUNTER 16-DIP

PHP16.67797

PHP15.01017

From: PHP16.67797

CD40110BE

DIP-16

Harris

Description: The CD40110BE is a CMOS 16-stage ripple-carry binary counter/divider and oscillator with three oscillator terminals (RS, RTC, and CTC) and an overriding asynchronous master reset (MR) inp

Display Counter

Utsource

≥1:

PHP74.83237

PHP67.34913

≥5:

PHP49.88822

PHP44.89942

≥10:

PHP44.89942

PHP40.40946

≥20:

PHP43.65224

PHP39.28703

≥50:

PHP42.40498

PHP38.16444

≥100:

PHP41.15780

PHP37.04201

≥200:

PHP39.91062

PHP35.91959

≥500:

PHP39.41170

PHP35.47053

≥1000:

PHP38.66336

PHP34.79699

From: PHP38.66336

CD4040BCN

DIP-16

FSC

Utsource

≥1:

PHP49.88822

PHP44.89942

≥5:

PHP37.41618

PHP33.67456

≥10:

PHP26.19133

PHP23.57222

≥20:

PHP24.94415

PHP22.44971

≥50:

PHP22.44971

PHP20.20477

≥100:

PHP21.82579

PHP19.64322

≥200:

PHP21.20253

PHP19.08226

≥500:

PHP20.57919

PHP18.52130

≥1000:

PHP19.95527

PHP17.95975

From: PHP19.95527

CD4020BCM

SOP

FAI

99+

Description: The CD4020BCM is a 14-stage ripple-carry binary counter/divider and oscillator. Features: High Speed Operation Low Power Consumption Wide Operating Temperature Range Low Input

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or

Utsource Original Store

≥3:

PHP28.01898

PHP25.21708

≥50:

PHP25.68407

PHP23.11566

≥100:

PHP23.34915

PHP21.01424

From: PHP23.34915

74F160APC

DIP-16

FSC

00+

Utsource

≥1:

PHP127.17858

PHP114.46071

≥5:

PHP84.78569

PHP76.30711

≥10:

PHP76.30720

PHP68.67645

≥20:

PHP74.18785

PHP66.76907

≥50:

PHP72.06791

PHP64.86111

≥100:

PHP69.94789

PHP62.95307

≥200:

PHP67.82862

PHP61.04578

≥500:

PHP66.98071

PHP60.28267

≥1000:

PHP65.70927

PHP59.13832

From: PHP65.70927

CD4040BCN

DIP

Fairchild

9824+

Description: The CD4040BCN is a CMOS 12-stage ripple carry binary counter/divider and oscillator. Features: High speed operation Low power consumption High noise immunity High output drive capabi

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or

Utsource Original Store

≥1:

PHP150.10169

PHP135.09152

≥5:

PHP100.06780

PHP90.06102

≥10:

PHP90.06102

PHP81.05491

≥20:

PHP87.55932

PHP78.80339

≥50:

PHP85.05763

PHP76.55186

≥100:

PHP82.55593

PHP74.30034

≥200:

PHP80.05424

PHP72.04881

≥500:

PHP79.05356

PHP71.14820

≥1000:

PHP77.55254

PHP69.79729

From: PHP77.55254

SN74HC161N

DIP16

HLF

18+

IC 4-BIT BINARY COUNTER 16-DIP

PHP14.59322

PHP13.13390

From: PHP14.59322
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