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1. Utsource will inspect the goods, including appearance inspection (no serious damage to the appearance), select qualified and honest suppliers, and ensure 98% qualification rate.
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Description
Nonvolatile Timekeeping RAM
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FEATURES
● Form, fit, and function compatible with the MK48T08 Timekeeping RAM
● Integrated NV SRAM, real time clock, crystal, power-fail control circuit and lithium energy source
● Standard JEDEC bytewide 8K x 8 static RAM pinout
● Clock registers are accessed identical to the static RAM. These registers are resident in the eight top RAM locations.
● Totally nonvolatile with over 10 years of operation in the absence of power
● Access times of 120 ns and 150 ns
● Quartz accuracy ±1 minute a month @ 25℃, factory calibrated
● BCD coded year, month, date, day, hours, minutes, and seconds with leap year compensation valid up to 2100
● Power-fail write protection allows for ±10% VCC power supply tolerance
DESCRIPTION
The DS1643 is an 8K x 8 nonvolatile static RAM with a full function real time clock which are both accessible in a bytewide format. The nonvolatile time keeping RAM is pin and function equivalent to any JEDEC standard8K x 8 SRAM. The device can also be easily substituted in ROM, EPROM and EEPROM sockets providing read/write nonvolatility and the addition of the real time clock function. The real time clock information resides in the eight uppermost RAM locations. The RTC registers contain year, month, date, day, hours, minutes, and seconds data in 24 hour BCD format. Corrections for the day of the month and leap year are made automatically.
The RTC clock registers are double buffered to avoid access of incorrect data that can occur during clock up-date cycles. The double buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1643 also contains its own power–fail circuitry which deselects the device when the VCC supply is in an out of tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided.
CLOCK OPERATIONS–READING THECLOCK
While the double buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1643 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a one is written into the read bit, the seventh most significant bit in the control register. As long as a one remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that is day, date, and time that was current at the moment the halt command was issued. However, the internal clock registers of the double buffered system continue to update so that the clock accuracy is not affected by the access of data. All of the DS1643 registers are updated simultaneously after the clock status is reset. Updating is within a second after the read bit is written to zero.
Preview of the first 3 pages of the data sheet
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282 buyer reviews from Canada
Matthew Anderson
Length of registration:7 years
I recently purchased the DS1643-100 integrated circuit from Utsource and I am very pleased with the product. The chip arrived quickly and was well packaged. After testing the chip, I found that it performed exactly as expected and was of very high quality. The chip was also very easy to use and I had no issues with installation. I would highly recommend Utsource and the DS1643-100 integrated circu
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03/17/2023
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DS1643-100
DS1643-100 has several brands around the world that may have alternate names for DS1643-100 due to regional differences or acquisition. DS1643-100 may also be known as the following names:
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Unit Price:6.91542
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