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国家代码DIP20
Ns/fsc
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with an enable input. The 'LS377, 'LS378, and 'LS379 devices are similar to 'LS273, 'LS174, and 'LS175, respectively, but feature a common enable instead of a common clear. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G\ input. These flip-flops are guaranteed to respond to clock frequencies ranging from 0 to 30 MHz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 10 milliwatts per flip-flop.
库存:10000
起订量:2
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SOP-20
TI9
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with an enable input. The 'LS377, 'LS378, and 'LS379 devices are similar to 'LS273, 'LS174, and 'LS175, respectively, but feature a common enable instead of a common clear. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G\ input. These flip-flops are guaranteed to respond to clock frequencies ranging from 0 to 30 MHz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 10 milliwatts per flip-flop.
库存:10000
起订量:3
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DIP24
Texas Instruments
00+
ti SN74ALS577A, Octal D-type Edge-triggered Flip-flops With 3-State Outputs
Description: The SN74ALS577ANT is a high-speed, low-power, octal D-type flip-flop with 3-state outputs. Features: * Low power consumption * High-speed operation * 3-state outputs * TTL-compatible inp
库存:10000
起订量:2
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SOP-20
FSC
Octal D Flip-Flop with Clear; Package: SOIC-Wide; No of Pins: 20; Container: Rail
库存:10000
起订量:6
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DIP20
TI Texas Instruments
1547+
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with an enable input. The 'LS377, 'LS378, and 'LS379 devices are similar to 'LS273, 'LS174, and 'LS175, respectively, but feature a common enable instead of a common clear. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G\ input. These flip-flops are guaranteed to respond to clock frequencies ranging from 0 to 30 MHz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 10 milliwatts per flip-flop.
Description: The CD74FCT374E is a high-speed CMOS Octal D-type Flip-Flop with 3-state outputs fabricated with silicon gate CMOS technology. Features: High Speed Operation: tPD = 10ns (typ) at VCC =
库存:10000
起订量:2
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DIP-16
MIT
82
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with an enable input. The 'LS377, 'LS378, and 'LS379 devices are similar to 'LS273, 'LS174, and 'LS175, respectively, but feature a common enable instead of a common clear. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G\ input. These flip-flops are guaranteed to respond to clock frequencies ranging from 0 to 30 MHz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 10 milliwatts per flip-flop.
Description: Dual Monostable Multivibrator Features: High Voltage Type (20V Rating) Outputs Source/Sink 24mA Retriggerable Output Pulse Width Control by Two External Resistors and Capacitor Input
库存:10000
起订量:4
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SOP20
1140+
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with an enable input. The 'LS377, 'LS378, and 'LS379 devices are similar to 'LS273, 'LS174, and 'LS175, respectively, but feature a common enable instead of a common clear. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G\ input. These flip-flops are guaranteed to respond to clock frequencies ranging from 0 to 30 MHz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 10 milliwatts per flip-flop.
库存:10000
起订量:4
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DIP-16
FSC
0516+
16-Bit Buffer/Line Driver with 3-STATE Outputs; Package: SSOP; No of Pins: 48; Container: Tape & Reel
库存:10000
起订量:3
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Description: Quad D-Type Flip-Flop Features: Low Power Consumption Low Input Current High Noise Immunity High Speed Performance Outputs Source/Sink 24 mA Inputs Accept Voltages to 5
库存:10000
起订量:4
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SOP14
Ns/fsc
00+
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with an enable input. The 'LS377, 'LS378, and 'LS379 devices are similar to 'LS273, 'LS174, and 'LS175, respectively, but feature a common enable instead of a common clear. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G\ input. These flip-flops are guaranteed to respond to clock frequencies ranging from 0 to 30 MHz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 10 milliwatts per flip-flop.
库存:10000
起订量:13
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SOT-363/MAA06A
Fairchild
05+
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with an enable input. The 'LS377, 'LS378, and 'LS379 devices are similar to 'LS273, 'LS174, and 'LS175, respectively, but feature a common enable instead of a common clear. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G\ input. These flip-flops are guaranteed to respond to clock frequencies ranging from 0 to 30 MHz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 10 milliwatts per flip-flop.
Description: NC7SZ175P6X is a single inverter gate from Fairchild Semiconductor. It is a low-power, low-voltage, single-gate CMOS device. Features: - Low power consumption - Low voltage operation - H
库存:10000
起订量:13
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SOT-363/MAA06A
Fairchild
05
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with an enable input. The 'LS377, 'LS378, and 'LS379 devices are similar to 'LS273, 'LS174, and 'LS175, respectively, but feature a common enable instead of a common clear. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G\ input. These flip-flops are guaranteed to respond to clock frequencies ranging from 0 to 30 MHz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 10 milliwatts per flip-flop.
Description: NC7SZ175P6X is a single inverter gate from Fairchild Semiconductor. It is a low-power, low-voltage, single-gate CMOS device. Features: - Low power consumption - Low voltage operation - H
库存:10000
起订量:13
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SOP8
STMicroelectronics
07+
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with an enable input. The 'LS377, 'LS378, and 'LS379 devices are similar to 'LS273, 'LS174, and 'LS175, respectively, but feature a common enable instead of a common clear. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G\ input. These flip-flops are guaranteed to respond to clock frequencies ranging from 0 to 30 MHz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 10 milliwatts per flip-flop.
Description: Quad 2-Input NAND Schmitt Trigger Features: - Low power Schottky technology - High noise immunity - High input impedance - Low input current - Outputs source/sink up to 20 mA - TTL compa
库存:10000
起订量:4
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Description: Dual D-Type Flip-Flop Features: - High-speed performance - Low power consumption - Inputs and outputs are TTL compatible - Outputs can be wired ORed Applications: - Frequency dividers -
库存:10000
起订量:5
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DIP-14
National Semiconductor
Dual D Positive-Edge-Triggered Flip-Flops with Preset and Clear; Package: DIP; No of Pins: 14; Container: Rail
库存:10000
起订量:2
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Description: Hex D-Type Flip-Flop Features: High-Voltage Types (20V Rating) Input Clamp Diodes Limit High-Level Input Voltage to VCC + 0.5V Outputs Source/Sink 24 mA Output Clamp Diodes Limi
库存:10000
起订量:2
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SOP
FSC
02+
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with an enable input. The 'LS377, 'LS378, and 'LS379 devices are similar to 'LS273, 'LS174, and 'LS175, respectively, but feature a common enable instead of a common clear. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G\ input. These flip-flops are guaranteed to respond to clock frequencies ranging from 0 to 30 MHz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 10 milliwatts per flip-flop.
Description: Dual D-Type Flip-Flop Features: High-Voltage Types (20V Rating) Medium Speed Operation Outputs Source/Sink 24mA Schmitt Trigger Inputs Input Clamping Diodes Standardized Symmetrical
库存:10000
起订量:3
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Description: The 74ACT11074N is a high-speed CMOS octal D-type flip-flop with 3-state outputs fabricated with TI's advanced silicon-gate CMOS technology. Features: High-speed performance: tPD = 11.
库存:10000
起订量:2
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The 74C74 is a dual D-type flip-flop with a clock and clear inputs. It is a 14-pin dual in-line package (DIP-14) manufactured by Texas Instruments (TI) and National Semiconductor (NS). Description: T
库存:10000
起订量:3
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DIP20
These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with an enable input. The 'LS377, 'LS378, and 'LS379 devices are similar to 'LS273, 'LS174, and 'LS175, respectively, but feature a common enable instead of a common clear. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G\ input. These flip-flops are guaranteed to respond to clock frequencies ranging from 0 to 30 MHz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 10 milliwatts per flip-flop.
库存:10000
起订量:2
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