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SN74LS74ANSR These devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the D input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.
The SN54' family is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74' family is characterized for operation from 0°C to 70°C.
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Description

These devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the D input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs. The SN54' family is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74' family is characterized for operation from 0°C to 70°C.

Not found, similar datasheet recommended

Title

Dual D-type pos.-edge-triggered flip-flops with preset and clear

  • ECAD Module
  • Series: 74LS
  • Brand: Texas Instruments
  • DateCode: 05
  • Package / Case: SOP-14
  • Packaging: Tape & Reel (TR)
  • Part Status: Active
  • Function: Set(Preset) and Reset
  • Type: D-Type
  • Output Type: Differential
  • Number of Elements: 2
  • Number of Bits per Element: 1
  • Clock Frequency: 33MHz
  • Max Propagation Delay @ V, Max CL: 40ns @ 5V, 15pF
  • Trigger Type: Positive Edge
  • Current - Output High, Low: 400μA, 8mA
  • Voltage - Supply: 4.75 V ~ 5.25 V
  • Current - Quiescent (Iq): 8mA
  • Operating Temperature: 0°C ~ 70°C (TA)
  • Mounting Type: Surface Mount

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ECAD Module

Product Attributes

  • SN74LS74ANSR is a dual D-type flip-flop with set and reset logic gates from Texas Instruments. It is a 14-pin small-outline package (SOP) device. Description: The SN74LS74ANSR is a dual D-type flip-flop with set and reset logic gates. It has two independent D-type flip-flops with separate data, set, reset, and clock inputs. The outputs change state on the positive going edge of the clock pulse. The set and reset inputs override the clock and data inputs, and are active low. Features: Dual D-type flip-flop with set and reset logic gates Separate data, set, reset, and clock inputs Outputs change state on the positive going edge of the clock pulse Set and reset inputs override the clock and data inputs Active low set and reset inputs 14-pin small-outline package (SOP) Applications: The SN74LS74ANSR is used in applications such as digital logic circuits, counters, and shift registers. It can also be used as a memory element in a computer system. (For reference only)

Preview of the first 3 pages of the data sheet

  • SN74LS74ANSR's pdf picture 1
  • SN74LS74ANSR's pdf picture 2
  • SN74LS74ANSR's pdf picture 3

Document Preview

SN74LS74A, SN74S74 DUAL DTYPE POSITIVEEDGETRIGGERED FLIPFLOPS WITH PRESET AND CLEAR

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

SN74LS74A, SN74S74 DUAL DTYPE POSITIVEEDGETRIGGERED FLIPFLOPS WITH PRESET AND CLEAR
SN74LS74A, SN74S74 DUAL DTYPE POSITIVEEDGETRIGGERED FLIPFLOPS WITH PRESET AND CLEAR

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    • SN74LS74ANSR These devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the D input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs. The SN54' family is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74' family is characterized for operation from 0°C to 70°C.
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